1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof and more particularly, to an insulation layer structure and a method of making the insulation layer structure for a semiconductor device.
2. Background of the Related Art
In order to form a dual thickness gate insulation layer for a dual gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an ion implanting method or an etching method is used. The ion implanting methods use either nitrogen or fluorine. The nitrogen ion implanting method is used to form a relatively thin gate insulation layer, while the fluorine ion implanting method is employed to form a relatively thick gate insulation layer. However, gate insulation layers formed by nitrogen ion implanting tend to have a relatively poor reliability, while gate insulation layers formed by fluorine ion implanting may exhibit increased junction leakage current since fluorine defects are formed around junctions of fluorine ion implanted gate insulation layers.
A dual thickness insulation layer may be formed using a dry etching technique or a wet etching technique. FIGS. 1A through 1D are cross-sectional views sequentially illustrating process steps in the formation of a background dual thickness insulation layer, for a semiconductor device, using a dry etching method. As shown in FIG. 1A, a first insulation layer 12 is formed on a semiconductor substrate 11. A first gate electrode layer 13 is formed on the first insulation layer 12. A first photoresist pattern 14 is then formed on the first gate electrode layer 13. See FIG. 1B. Using the first photoresist pattern 14 as a mask in a dry etching method, the first gate electrode layer 13 and the first insulation layer 12 are sequentially removed to form a first gate electrode layer pattern 13a and a first gate insulation layer pattern 12a.
After removing the first photoresist pattern 14, as shown in FIG. 1C, a second insulation layer 15 is formed on the semiconductor substrate 11, the first gate electrode layer pattern 13a, and the first gate insulation layer pattern 12a. The second insulation layer 15 is formed thicker (or thinner) than the first insulation layer 12 such that the first insulation layer 12 and the second insulation layer 15 have different thicknesses. A second gate electrode layer 16 is formed on the second insulation layer 15. A second photoresist pattern 17 is formed on the second gate electrode layer 16.
As shown in FIG. 1D, using the second photoresist pattern 17 as a mask, the second gate electrode layer 16 and the second insulation layer 15 are sequentially removed, by a dry etching method, to form a second gate electrode layer pattern 16a and a second gate insulation layer pattern 15a. Thereafter, the second photoresist pattern 17 is removed.
The method of FIGS. 1A-1D is disadvantageous since formation of the first and second insulation layers having different thicknesses using a dry etching process requires highly complicated fabrication steps. Further, when the first gate electrode layer pattern 13a needs to be doped by ion implanting, the first gate electrode layer pattern 13a absorbs more heat than does the second gate electrode layer pattern 15a, resulting in decreased product reliability. Furthermore, use of a dry etching method for the formation of the dual thickness insulation layer may result in a damaged semiconductor device.
FIGS. 2A through 2C are cross-sectional views sequentially illustrating process steps in a background method of forming a dual thickness insulation layer for a semiconductor device using a wet etching method. In FIG. 2A, a first oxide layer 23 serving as an insulation layer is formed on a semiconductor substrate 21. A first photoresist pattern 25 is formed on the first insulation layer 23. As shown in FIG. 2B, using the first photoresist pattern 25 as a mask, the first oxide layer 23 is etched using a wet etching method, and the first photoresist pattern 25 is removed. As further shown in FIG. 2C, in order to form a dual thickness insulation layer, a second oxide layer 27 is grown on the first oxide layer 23 and the exposed semiconductor substrate 21.
The method of FIGS. 2A-2C is disadvantageous due to numerous repetitions of the growing step and the etching step which may be needed to form the dual thickness insulation layer and it may be difficult to form the required thickness of the insulation layer. Further, the gate insulation layer may be subject to damage when removing the photoresist pattern. Still further, in the case of a relatively thick gate insulation layer, the gate insulation layer should be grown twice for its formation, thereby deteriorating the product reliability.